As multi-core technologies develop, a system becomes increasingly complex, and interactive events between multiple cores are increasing. In the prior art, processing of synchronization and communication between the multiple cores is typically completed through interrupts.
In the prior art, during processing of event synchronization between the multiple cores, when multiple processors apply for a same mutually exclusive cache inside a semaphore processing unit at the same time, the multiple processors here refer to the multiple cores and the multiple processors and the semaphore processing unit are located on a system on chip (SOC), and the mutually exclusive cache is a caching resource that can only be used by one processor at a certain moment. Typically, the semaphore processing unit sends, through an interrupt and to a processor A among the processors, an identifier for acquiring the caching resource, and after responding to the interrupt and completing event processing, the processor A clears the interrupt. Then, the semaphore processing unit sends the acquisition identifier of the caching resource to another processor through an interrupt.
In the prior art, during processing of message synchronization between the multiple cores, as for that the processor A in the multiple cores applies for a message channel X inside an inter-process communications (IPC) processing unit, after the processor A writes a message onto the message channel X, and the IPC processing unit notifies, through an interrupt, processors other than the processor A which need to acquire the message. In this case, the other processors respond to the interrupt, read the message on the message channel X, and then clear the interrupt.
However, in the prior art, when synchronization and communication between the multiple cores are processed, typically, a synchronization operation needs to be completed through an interrupt, which leads to low efficiency in system scheduling and consumption of considerable resources.